Xilinx Design Summary

TELE Partition Summary
No partition information was found.

Device Utilization Summary
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	21	1,920	1%
Number of 4 input LUTs	18	1,920	1%
Logic Distribution
Number of occupied Slices	22	960	2%
Number of Slices containing only related logic	22	22	100%
Number of Slices containing unrelated logic	0	22	0%
Total Number of 4 input LUTs	36	1,920	1%
Number used as logic	18
Number used as a route-thru	18
Number of bonded IOBs	18	83	21%
Number of Block RAMs	2	4	50%
Number of GCLKs	1	24	4%
Total equivalent gate count for design	131,465
Additional JTAG gate count for IOBs	864

Performance Summary
Final Timing Score:	0	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met