TELE Project Status
Project File: | tele.ise | Current State: | Programming File Generated
Module Name: | premiertp | Errors: | No Errors
Target Device: | xc3s100e-5cp132 | Warnings: | 30 Warnings
Product Version: | ISE 9.2.04i | Updated: | mer. 4. avr. 09:01:19 2012

TELE Partition Summary
No partition information was found.

Device Utilization Summary
Logic Utilization | Used | Available | Utilization | Note(s)
Number of Slice Flip Flops | 21 | 1,920 | 1% |
Number of 4 input LUTs | 18 | 1,920 | 1% |
Logic Distribution |  |  |  |
Number of occupied Slices | 22 | 960 | 2% |
Number of Slices containing only related logic | 22 | 22 | 100% |
Number of Slices containing unrelated logic | 0 | 22 | 0% |
Total Number of 4 input LUTs | 36 | 1,920 | 1% |
Number used as logic | 18 |  |  |
Number used as a route-thru | 18 |  |  |
Number of bonded IOBs | 18 | 83 | 21% |
Number of Block RAMs | 2 | 4 | 50% |
Number of GCLKs | 1 | 24 | 4% |
Total equivalent gate count for design | 131,465 |  |  |
Additional JTAG gate count for IOBs | 864 |  |  |

Performance Summary
Final Timing Score: | 0 | Pinout Data: | Pinout Report
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report
Timing Constraints: | All Constraints Met |  |

Detailed Reports
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | mer. 4. avr. 08:59:16 2012 | 0 | 1 Warning | 0
Translation Report | Current | mer. 4. avr. 09:00:29 2012 | 0 | 0 | 0
Map Report | Current | mer. 4. avr. 09:00:41 2012 | 0 | 22 Warnings | 3 Infos
Place and Route Report | Current | mer. 4. avr. 09:01:01 2012 | 0 | 0 | 2 Infos
Static Timing Report | Current | mer. 4. avr. 09:01:08 2012 | 0 | 0 | 3 Infos
Bitgen Report | Current | mer. 4. avr. 09:01:18 2012 | 0 | 7 Warnings | 0